1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and, more particularly, to a bipolar (ECL) integrated circuit having an improved .alpha.-ray-resistant property.
2. Description of the Prior Art
FIG. 2. is a circuit diagram showing a D latch circuit published in IEEE ISSCC, Digest of Technical Papers, p 178-179, February 1982. Referring to the Figure, designated at 3D is a latch circuit, at D1 and D2 data inputs, C1 and C2 clock inputs, at R a reset input, at Y a non-inverted latch output, and Y an inverted latch output.
FIG. 3 is a circuit diagram showing a prior art D latch circuit based on an ECL series gate circuit construction shown in the papers noted above. In the Figure, designated at D1 and D2 are data inputs, at C1 and C2 clock inputs, at R a reset input, at Y a non-inverted latch output, and at Y an inverted latch output. Designated at Q31 to Q39, Q3a and Q3b NPN transistors, Q3c and Q3d NPN double emitter transistors, and R30 to R39 and R3a resistors.
This circuit has a two-stage series gate structure. Designated at VBB1 and VBB2 are reference voltages, at VBB1 a high potential side reference voltage, at VBB2 a low potential side reference voltage, and at Vcs a reference voltage to the current source transistor Q3b.
Now, the operation will be explained. It is assumed that the reset input R is at a low level because this has no essential relation to the description hereinafter. It is now assumed the two clock inputs C1 and C2 are at a low level. At this time, the transistor Q39 is "off" while the transistor Q3a is "on". Thus, the OR logic of the data inputs, i.e., D1+D2, appears at the output Y, while the output Y is D1+D2. For example, when both the inputs D1 and D2 are at low level, the output Y is at a low level while the output Y is at a high level.
When at least one of the clock inputs C1 and C2 goes to a high level, the transistor Q39 which has been "off" is turned on while the transistor Q3a which has been "on" is turned off. As a result, the switching current Is flows from through the current source transistor Q3b to through the transistor Q39. Since the output Y is at low level, the potential at the node N31 is also at low level. Also, since the output Y is at high level, the potential at the node N32 is at high level.
From the above, it is apparent that the switching current Is flows through the transistors Q39 and Q37. Also, due to the voltage drops across the resistors R30 and R32, the potential at the node N31 is at low level. Thus, the output Y is held at low level, and the output Y at high level. Thus, even when one of the data inputs D1 and D2 is changed to high level, the switching current Is never flows through the transistors Q31 and Q32. Thus, the output is held unchanged. That is, the output is held latched. In other words, the above circuit constitutes a latch circuit.
Recently, semiconductor elements have been made fine to such an extent that soft errors due to .alpha.-particles generated from packages or the like can not be ignored. Soft errors will now be described with reference to FIG. 3.
Now assume that the output Y is held at high level and the output Y at a low level (i.e., at least one of the clock inputs C1 and C2 is at high level). At this time, the transistor Q38 is "on", and the transistors Q36 and Q37 are "off". Thus, the nodes N30 and N32 are at low level, and the nodes N31 and N33 are at high level.
In this state, when one of the transistors Q33, Q36 and Q37 connected to the node N31 is irradiated with .alpha.-rays, electron-hole pairs are generated. When the electrons are collected in the collector area, the collector potential, i.e., the potential on the node N31 is momentarily reduced. To make up for this reduction, charging is done from the power source Vcc through the resistors R30 and R32. Therefore, even if the pulse width is minimum, a spike-like pulse of several hundred picoseconds is generated. This pulse is transmitted as noise to the node N33 and fed back to the base of the transistor Q38. Therefore, the transistor Q38 which has been "on" is cut off, while the transistor Q37 is turned on. The contents of the data that has been held are thus inverted.
The spike noise that is generated by such .alpha.-rays is substantially inversely proportional to the capacitance accompanying the collector of the transistor. For this reason, future soft errors due to semiconductor element size reduction are inevitable.
The prior art ECL sequential circuit has a problem of inversion of the held data due to .alpha.-rays. To solve this problem it has been proposed to add capacitance to the transistor of the data holding circuit (as disclosed in Japanese Patent Kokai No. 60-142619) or increase current (as disclosed in Japanese Patent Kokai No. 60-143019). In these methods, however, there is a delay time in the sequential circuit or increase of power consumption.